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 FAST CMOS BUFFER/CLOCK DRIVER
Integrated Device Technology, Inc.
IDT49FCT3805/A
FEATURES:
* * * * * * * * * * 0.5 MICRON CMOS Technology Guaranteed low skew < 500ps (max.) Very low duty cycle distortion < 1.0ns (max.) Very low CMOS power levels TTL compatible inputs and outputs Inputs can be driven from 3.3V or 5V components Two independent output banks with 3-state control 1:5 fanout per bank `Heartbeat' monitor output Available in DIP, SOIC, SSOP, QSOP, Cerpack and LCC packages * Military product compliant to MIL-STD-883, Class B * VCC = 3.3V 0.3V
DESCRIPTION:
The FCT3805/A is a 3.3 volt, non-inverting clock driver built using advanced dual metal CMOS technology. The device consists of two banks of drivers, each with a 1:5 fanout and its own output enable control. The device has a "heartbeat" monitor for diagnostics and PLL driving. The MON output is identical to all other outputs and complies with the output specifications in this document. The FCT3805/A offers low capacitance inputs with hysteresis. The FCT3805/A is designed for high speed clock distribution where signal quality and skew are critical. The FCT 3805 also allows single point-to-point transmission line driving in applications such as address distribution, where one signal must be distributed to multiple receivers with low skew and high signal quality.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
VCCA OA1 1 2 3 4 5 6 7 8 9 10 P20-1 D20-1 SO20-2 SO20-7 SO20-8 & E20-1 20 19 18 17 16 15 14 13 12 11 VCCB OB1 OB2 OB3 GNDB OB4 OB5 MON OEB INB
3102 drw 02
OEA
OA2 OA3
5 OA1-OA5
GNDA OA4 OA5
INA
INB
5
OB1-OB5
GNDQ OEA
OEB MON
3102 drw 01
INA
DIP/SOIC/SSOP/QSOP/CERPACK TOP VIEW
VCCA VCCB OA2 OA1
INDEX
3 OA3 GNDA OA4 OA5 GNDQ 4 5 6 7 8
2
1
20 19 18 17 OB2 OB3 GNDB OB4 OB5
OB1
L20-2
16 15 14
9 10 11 12 13
OEA OEB INA INB MON
3102 drw 03
LCC TOP VIEW
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(c)1996 Integrated Device Technology, Inc.
OCTOBER 1995
DSC-3102/4
9.5
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IDT49FCT3805/A FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Pin Names
FUNCTION TABLE(1)
Inputs Outputs INA, INB L H L H OAn, OBn L H Z Z MON L H L H
3102 tbl 02
OEA, OEB
INA, INB OAn, OBn MON
Description 3-State Output Enable Inputs (Active LOW) Clock Inputs Clock Outputs Monitor Output
3102 tbl 01
OE OE OEA, OEB
L L H H
NOTE: 1. H = HIGH, L = LOW, Z = High Impedance
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Rating VTERM(2) Terminal Voltage with Respect to GND VTERM(3) Terminal Voltage with Respect to GND VTERM(4) Terminal Voltage with Respect to GND TA Operating Temperature TBIAS Temperature Under Bias TSTG Storage Temperature IOUT DC Output Current Commercial Military -0.5 to +4.6 -0.5 to +4.6 Unit V
CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol Parameter(1) CIN Input Capacitance COUT Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 3.5 3.5 Max. Unit 5.0 pF 5.0 pF
3102 lnk 04
-0.5 to +7.0
-0.5 to +7.0
V
-0.5 to VCC + 0.5 0 to +70 -55 to +125 -55 to +125 -60 to +60
-0.5 to VCC + 0.5 -55 to +125 -65 to +135 -65 to +150 -60 to +60
V C C C mA
NOTE: 1. This parameter is measured at characterization but not tested.
3102 lnk 03 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Vcc terminals. 3. Input terminals. 4. Output and I/O terminals.
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IDT49FCT3805/A FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0C to +70C, VCC = 3.3V 0.3V; Military: TA = -55C to +125C, VCC = 3.3V 0.3V
Symbol VIH VIL II H II L IOZH IOZL VIK IODH IODL VOH Parameter Input HIGH Level (Input pins) Input HIGH Level (I/O pins) Input LOW Level (Input and I/O pins) Input HIGH Current (Input pins)(6) Input HIGH Current (I/O pins)(6) pins)(6) VCC = Max. Input LOW Current (Input VCC = Max. VI = 5.5V VI = VCC VI = GND VI = GND VO = VCC VO = GND VCC = Min., IIN = -18mA VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3) VCC = 3.3V, VIN = VIH or VIL, VO = VCC = Min. VIN = VIH or VIL VOL Output LOW Voltage VCC = Min. VIN = VIH or VIL IOFF IOS VH ICCL ICCH ICCZ Input Power Off Leakage (6) Short Circuit Current(4) Input Hysteresis Quiescent Power Supply Current VCC = Max., VIN = GND or VCC VCC = 0V, VIN 4.5V VCC = Max., VO = GND(3)
--
Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level
Min. 2.0 2.0 -0.5 -- -- -- -- -- -- -- -36 50 VCC-0.2 2.4 (5) -- -- -- -- -60 -- -- -- 1.5V(3)
Typ.(2) -- -- -- -- -- -- -- -- -- -0.7 -60 90 -- 3.0 -- 0.2 0.3 -- -135 150 0.1 0.1
Max. 5.5 VCC+0.5 0.8 1 1 1 1 1 1 -1.2 -110 200 -- -- 0.2 0.4 0.50 1 -240 -- 10 100
Unit V V A
Input LOW Current (I/O pins)(6) High Impedance Output Current (3-State Output pins) (6) Clamp Diode Voltage Output HIGH Current Output LOW Current Output HIGH Voltage
A V mA mA V
IOH = -0.1mA IOH = -6mA MIL. IOH = -8mA COM'L. IOL = 0.1mA IOL = 16mA IOL = 24mA
V
A mA mV A
COM'L. MIL.
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 3.3V, +25C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. This parameter is guaranteed but not tested. 5. VOH = VCC -0.6V at rated current. 6. The test limit for this parameter is 5A at TA = -55C.
3102 lnk 05
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IDT49FCT3805/A FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current (4) Test Conditions(1) VCC = Max. VIN = VCC -0.6V(3) VCC = Max. Outputs Open OEA = OEB = GND Per Output Toggling 50% Duty Cycle VCC = Max. Outputs Open fo = 25MHz 50% Duty Cycle OEA = OEB =VCC Mon. Output Toggling VCC = Max. Outputs Open fo = 50MHz 50% Duty Cycle OEA = OEB = GND Eleven Outputs Toggling VIN = VCC VIN = GND Min. -- -- Typ.(2) 2.0 0.035 Max. 30 0.06 Unit A mA/ MHz
IC
Total Power Supply Current (6)
VIN = VCC VIN = GND VIN = VCC -0.6V VIN = GND VIN = VCC VIN = GND VIN = VCC -0.6V VIN = GND
--
0.9
1.6
mA
--
0.9
1.6
--
20.0
33.0 (5)
--
20.0
33.0 (5)
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25C ambient. 3. Per TTL driven input (VIN = VCC -0.6V); all other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. 5. Values for these conditions are examples of the IC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fONO) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ICC = Power Supply Current for a TTL High Input (VIN = VCC -0.6V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fO = Output Frequency NO = Number of Outputs at fO All currents are in milliamps and all frequencies are in megahertz.
3102 tbl 06
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IDT49FCT3805/A FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE(3,4)
FCT3805 Com'l. Mil. Symbol Parameter tPLH Propagation Delay INA to OAn, INB to OBn tPHL tR Output Rise Time tF tSK(o) tSK(p) tSK(t) Output Fall Time Output skew: skew between outputs of all banks of same package (inputs tied together) Pulse skew: skew between opposite transitions of same output (|tPHL-t PLH|) Package skew: skew between outputs of different packages at same power supply voltage, temperature, package type and speed grade Output Enable Time OEA to OAn, OEB to OBn Output Disable Time OEA to OAn, OEB to OBn FCT3805A Com'l. Mil. Unit ns ns ns ns ns ns
Condition(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. CL = 50pF 1.5 5.8 1.5 5.0 RL = 500 -- 2.0 -- -- 2.0 -- -- -- -- -- 2.0 0.7 1.2 1.5 -- -- -- -- -- -- -- -- 2.0 0.5 1.0 1.2 -- -- -- --
tPZL tPZH tPLZ tPHZ
1.5 1.5
6.5 5.5
1.5 1.5
6.0 5.0
ns ns
3102 tbl 07 NOTES: 1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. tPLH, tPHL, tSK(t) production tested. All other parameters guaranteed but not production tested. 4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay limits do not imply skew.
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IDT49FCT3805/A FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS TEST CIRCUIT FOR ALL OUTPUTS
6.0V VCC 500 VIN Pulse Generator RT D.U.T. 50pF 500
3102 drw 04
ENABLE AND DISABLE TIME SWITCH POSITION
Test Disable LOW Enable LOW Disable HIGH Enable HIGH Switch 6.0V GND
GND
VOUT
3102 tbl 08 DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
PACKAGE DELAY
3V 1.5V INPUT tPLH tPHL VOH 2.0V OUTPUT tR tF
3102 drw 05
OUTPUT SKEW- tSK(o)
INPUT 3V 1.5V 0V VOH 1.5V VOL tSK(o) OUTPUT 2 tPLH2 tPHL2
3102 drw 06
0V
tPLH1
tPHL1
OUTPUT 1 tSK(o)
1.5V VOL
0.8V
VOH 1.5V VOL
tSK(o) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|
PULSE SKEW- tSK(p)
3V 1.5V 0V tPLH tPHL VOH 1.5V VOL
3102 drw 07
PACKAGE SKEW- tSK(t)
INPUT tPHL1 3V 1.5V 0V VOH 1.5V VOL VOH 1.5V VOL
tPLH1
INPUT
PACKAGE 1 OUTPUT tSK(t) PACKAGE 2 OUTPUT tSK(t)
OUTPUT tSK(p) = |tPHL - tPLH|
tPLH2
tPHL2
tSK(t) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|
ENABLE AND DISABLE TIMES
ENABLE CONTROL INPUT t OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH
PZL
3102 drw 08
DISABLE 3V 1.5V 0V t PLZ 3.5V 1.5V t 1.5V 0V 0V
3102 drw 09
SWITCH CLOSED t PZH SWITCH OPEN
3.5V 0.3V V OL
PHZ
0.3V
VOH
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH 2. Pulse Generator for All Pulses: f 1.0MHz; tF 2.5ns; tR 2.5ns
9.5
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IDT49FCT3805/A FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT 49FCT XXX Device Type XX Package X Process/ Temperature Range Blank B Commercial MIL-STD-883, Class B
P D E L SO PY Q 3805 3805A
Plastic DIP CERDIP CERPACK Leadless Chip Carrier Small Outline IC Shrink Small Outline IC Quarter-size Small Outline IC Non-Inverting 3.3V Buffer/Clock Driver
3102 drw 10
9.5
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